1. Field of the Invention
This invention generally relates to memory subsystems in a computer system such as cache memory, and, more specifically, relates to a memory subsystem placed between a CPU and a display controller that operates like a cache in relation to the CPU and operates like a dual port First In, First Out memory (FIFO) in relation to the display controller.
2. Description of the Related Art
Caches, write buffers, and read buffers have been extensively used to increase the performance of CPU bus transfers in computer systems. Caches are the most complicated and generally the most effective. However, they are designed to optimize CPU data and code accesses. This is often not an efficient design for use with a graphics controller.
Write buffers optimize write transfers. A graphics controller performs mostly write transfers, and hence can benefit from using a write buffer. Although write transfers encompass a significant portion of the graphics transfers, it is not effective for reads or read-modify-write cycles, which the graphics controller must also perform. Read buffers optimize read transfers. However, the memory associated with read buffers is not well utilized, since the read cycles comprise a minority of transfers done by a graphics controller.
The most common transfers for graphics controllers are sequential writes, sequential reads, sequential read-modify-writes, and sequential read-read-modify-writes. Today most CPU bus graphics controllers utilize a write buffer, and a few also have a read buffer. The write buffer will accommodate the sequential write cycles, the read buffer will accommodate the sequential read cycles, and the combination of the write buffer and the read buffer will accommodate the rest of the cycles. The critical problem is that using both a write buffer and a read buffer takes up a substantial amount of silicon, since each buffer must have its own dedicated memory. Thus the size of the memories associated with these write and read buffers causes for an inefficient use of silicon.
A cache memory is best suited to solve the problem of having double the memory associated with having both a write buffer and a read buffer, since the memory in a cache can be used as a read or a write location. A cache memory would thus take substantially less silicon to implement. However, a typical VGA graphics controller contains a modifying write path. This means that data would be read by the graphics controller, modified, and written back to the cache. Most cache architectures are not suited to handle this modifying feature that occurs in a highly sequential nature in graphics controllers. In addition, standard caches used with CPUs are relatively complex.
Therefore, there existed a need to provide a memory subsystem for use with a graphics controller which is optimized for sequential transfers, which can easily handle the modifying write path during read-modify-write and read-read-modify-write cycles, which optimizes transfers to the CPU, and which is less complex than a standard cache due to the highly sequential nature of accesses associated with graphics controllers.